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Advantages of LED small pitch
Compared with other display technologies, LED display has the advantages of self illumination, excellent color restoration, high refresh rate, power saving and easy maintenance. The two characteristics of high brightness and large size can be achieved through splicing are decisive factors for the rapid growth of LED display in the past two decades. In the field of large screen outdoor display, there is no other technology to compete with LED display technology.
But in the past, LED display also has its lack, for example, the spacing between the packaged lamp beads is large, forming a low resolution, which is not suitable for indoor and close interval viewing. In order to improve the resolution, it is necessary to reduce the spacing between the lamp beads, but the reduction of the size of the lamp beads can improve the resolution of the whole screen, and the cost will rise rapidly. The high cost affects the large-scale commercial application of the small spacing LED display screen.
In recent years, with the help of the efforts of chip and package manufacturers, IC circuit manufacturers and screen manufacturers, the cost of single package devices is getting lower and lower, LED package devices are getting smaller and smaller, the pixel spacing of display screen is getting smaller and smaller, and the resolution is getting higher and higher, which makes the advantages of small spacing LED display screen in indoor large screen display more and more obvious.
At present, small spacing LED is mainly used in advertising media, stadiums, stage background, municipal engineering and other areas, and from time to time in transportation, broadcasting, military and other areas to open up the market. It is estimated that by 2018, the market scope will be close to 10 billion. It can be predicted that in the next few years, the small spacing LED display will expand market share from time to time and occupy the market space of DLP rear projection.
1、 The demand of LED chip for small space LED display
As the center of LED display, LED chip plays an important role in the development of small spacing led. The current achievements and future development of small spacing LED display depend on the unremitting efforts of chip end.
On the one hand, the indoor display screen point spacing gradually decreased from the early P4 to P1.5, P1.0, and p0.8 in development. Correspondingly, the size of lamp beads has been reduced from 3535 and 2121 to 1010. Some manufacturers have developed 0808 and 0606 sizes, even some are developing 0404 sizes.
As we all know, the reduction of package lamp bead size will inevitably request the reduction of chip size. At present, the surface product of blue-green chips for small spacing display screen is about 30mil2 in the market, and some chip factories have been mass producing chips of 25mil2 or even 20mil2.
On the other hand, a series of problems that affect the display quality have become prominent due to the decrease of the chip surface product and the brightness of the single core.
The first is the request for grayscale. Different from outdoor screen, the difficulty of indoor screen is not brightness but gray. At present, the brightness demand of indoor large spacing screen is about 1500cd / m2-2000cd / m2, the brightness of small spacing LED display screen is generally about 600cd / m2-800cd / m2, and the best brightness of display screen suitable for long-term attention is about 100cd / m2-300cd / m2.
At present, one of the problems of small spacing LED screen is "low brightness and low gray". That is, the gray level under low brightness is not enough. To achieve "low brightness and high gray", the current plan of package end is to use black bracket. Due to the weak reflection of the black bracket on the chip, the chip is requested to have enough brightness.
The second is the problem of showing the average. Compared with the conventional screen, the smaller the spacing, the darker the first scan, the lower the brightness and the redder, and the lower the gray unevenness. At present, aiming at the problems such as afterglow, first scan and low gray and red, the packaging end and IC control end have made efforts to effectively alleviate these problems, and the brightness average problem under low gray level has also been alleviated by point by point correction technology. However, as one of the sources of the problem, the chip side needs more efforts. In detail, the brightness average is better under the small current, and the divergence of parasitic capacitance is better.
The third is the issue of reliability. The current industry standard is that the allowable value of LED dead light rate is 1 / 10000, which is obviously not suitable for small spacing LED display. Due to the large pixel density of the small spacing screen and the close viewing interval, if there are 10000 dead lights, the effect is unbearable. In the future, the demand for dead light rate will be controlled at 1 / 100000 or even 1 / 1000000 to meet the demand for long-term use.
In general, the development of small spacing led puts forward the requirements for core segments: size reduction, relative brightness improvement, good brightness divergence under small current, good parasitic capacitance divergence and high reliability.
2、 Chip processing plan
1. Size reduction chip size reduction
Outwardly, it's the problem of size design. It seems that it can be dealt with only by designing a smaller size according to the demand. However, can the reduction of chip size stop indefinitely? Can the answer be determined. There are several reasons to limit the level of chip size reduction:
(1) Limitation of package processing. In the process of packaging, two factors limit the reduction of chip size. One is the restriction of suction nozzle. The short side of the chip must be larger than the inner diameter of the nozzle. At present, the inner diameter of the suction nozzle with cost performance is about 80um. The second is the limitation of welding wire. The first is that the pad, i.e. chip electrode, must be large enough, otherwise the reliability of the wire cannot be guaranteed, and the minimum electrode diameter reported in the industry is 45um; the second is that the spacing between the electrodes must be large enough, otherwise the two wires will inevitably interfere with each other.
(2) The limitation of chip processing. There are two limitations in the process of chip processing. One is the limitation of territory planning. In addition to the above restrictions on package end, electrode size and electrode spacing, electrode and mesa spacing, trace width and boundary line spacing of different layers all have their limitations. The current characteristics of chip, SD process ability and photolithography processing ability determine the detailed limits. Generally, the minimum distance from the p electrode to the edge of the chip is limited to more than 14 μ M.
The second is the limitation of the ability of crack processing. SD slicing + mechanical chipping process has limits, chip size is too small may not be able to crack. When the wafer diameter increases from 2 inches to 4 inches, or to 6 inches in the future, the difficulty of slicing will increase, that is to say, the chip size that can be processed will increase. Taking 4-inch chip as an example, if the short side length of the chip is less than 90 μ m and the aspect ratio is greater than 1.5:1, the loss of yield will increase significantly.
Based on the above reasons, the author boldly predicts that only when the chip size is reduced to 17mil2 can the chip design and processing approach the limit, and there is no room for reduction at all, unless the chip technology plan is greatly broken.
2. Brightness improvement
Brightness enhancement is the permanent theme of the chip. The chip factory improves the internal quantum effect by epitaxial program optimization and the external quantum effect by chip structure adjustment.
However, on the one hand, the reduction of chip size will inevitably lead to the reduction of light-emitting area and brightness of chip. On the other hand, the point spacing of the small spacing display screen is reduced, which reduces the brightness demand of the single chip. There is a complementary relationship between the two, but there should be a bottom line. At present, in order to reduce the cost of chip, the subtraction is mainly done in the structure, which usually pays the price of brightness reduction. Therefore, how to balance the trade-offs is a problem that the industry should pay attention to.
3. Divergence under small current
The so-called small current is relative to the current of conventional indoor and outdoor chip trial. As shown in the following figure, the I-V curve of the chip. The conventional indoor and outdoor chips work in the linear working area, with large current. The small gap LED chip needs to work in the non-linear working area near the zero point, and the current is relatively small.
In the non-linear working area, LED chips are affected by semiconductor switching threshold, and the difference between chips is more obvious. It is easy to see that the discreteness of non-linear work area is much greater than that of linear work area. This is the inherent challenge of the chip.
In order to solve this problem, the first method is to optimize the epitaxial direction, mainly to reduce the lower limit of the linear working area; the second is to optimize the chip beam splitting, to distinguish the chips with different characteristics.
4. Divergence of parasitic capacitance
At present, there is no condition to measure the capacitance of the chip directly. The relationship between capacitance characteristics and conventional measurement items is not clear, which is to be summarized by the employer. The direction of chip end optimization is to adjust the extension and refine the electrical grading, but the cost is high, so it is not recommended.
5. reliability
The reliability of chip end can be described by various parameters in the process of chip packaging and aging. But generally speaking, ESD and IR are the key factors that affect the reliability of the chip after it is put on the screen.
ESD refers to anti-static ability. According to IC industry reports, more than 50% of chip failures are related to ESD. In order to improve chip reliability, ESD must be improved. However, under the condition of the same epitaxial chip and the same chip structure, the smaller chip size will inevitably weaken the ESD capability. This is directly related to the current density and the capacitance characteristics of the chip, which is irresistible
IR refers to reverse leakage, usually measuring the reverse current value of the chip under a fixed reverse voltage. IR reflects the number of defects inside the chip. The larger the IR value is, the more defects are revealed in the chip.
In order to improve ESD capability and IR performance, more optimization must be made in epitaxial structure and chip structure. In chip grading, after strict grading specification, it can effectively eliminate the chips with weak ESD ability and IR performance, so as to improve the reliability of the chip on the screen.
Four, summary
To sum up, with the progress of science and the update of the period, LED display industry is developing more and more, but how to improve the effect of the display industry is still waiting for the employees to exert their wisdom and make continuous efforts from time to time.